Use associated hardware technology to speed up the verification process
Chip designers are under constant pressure to improve chip performance while minimizing costs simultaneously. One way to achieve this is to speed up the verification process – because verification is more than 70% of the entire chip design process, embracing tools and technology that results in faster verification is the requirement of hours.
Need for hardware assisted verification models
To meet the demands of the shortened development cycle, it is important for hardware and software on the chip which will be verified at the same time. Because software development cannot wait until the hardware aspects of the chip are developed, the design team needs to adopt a failed-safe way to verify the chip will function as intended as soon as the embedded software is run. It requires a design team to make work prototypes for software development as early as possible, and many before the end of the hardware design cycle.
Hardware Help Technology
Given time pressure to the market, the verification process has been far away. For many digital design engineers, there are several strong reasons for verifying hardware. Because performance is key, it is important for the verification system to provide the highest performance model and performance environment for SOC verification.
• Hardware acceleration techniques help overcome challenges meeting performance requirements for SOC verification.
• Writing SystemVerilog Testbench for certain designs can be very tiring, especially when testing the interactions between different blocks.
• By verifying hardware assisted, you don’t need to write testbench or worry about how the interface will be done.
• For example, to check whether the peripheral device functions as referred to, you can retrieve a physical or virtual peripheral device, connect it to the design and then use the device driver for the controller to do a function to see if the interface is functioning.
• As a number of vectors that can be run per second are substantial, you can ensure that the interaction between hardware and software as expected in a short time span
• Hardware accelerators allow you to use components like FPGA to build a hardware platform.
• Using embedded test benches, you can verify the help of hardware and environmental virtualization to speed up the verification process.
With the increasing size and complexity of the current SOC device, verification requires you to do a massive test that covers billions of cycles. Using advanced verification technology such as hardware assisted emulation systems, you can speed up the verification process and provide the highest performance:
• Modern emulation systems include a broad transactor portfolio and memory model that accelerates the development of the virtual system verification environment.
• The emulation system offers a comprehensive debug with full signal visibility and supports advanced use modes including power management verification and hybrid emulation
• With emulation, design-under-test (DUT) is usually represented in the emulator, while the chip environment can be provided by connections outside the emulator.
• By using a virtual bridge along with the virtual test environment, you can connect DUT via protocol-specific transactor to real device
• In addition, the system level debug component can also be used to understand high-level SOCS behavior.
Another way to improve the verification process is to use a physical prototype to meet time-to-market requirements.
• By utilizing the hardware-assisted system environment, prototyping allows the development of early software that is embedded, allowing hardware and software to droop away in front of the chip fabrication.
• You can shorten the design schedule and avoid expensive devices roll back through strict integrated use